Binary decision diagram

Results: 113



#Item
71A New Enhanced Constructive Decomposition and Mapping Algorithm Alan Mishchenko Xinning Wang

A New Enhanced Constructive Decomposition and Mapping Algorithm Alan Mishchenko Xinning Wang

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Source URL: www.bvsrc.org

Language: English - Date: 2003-03-28 23:46:48
72LUTMIN: FPGA Logic Synthesis with MUX-Based and Cascade Realizations Tsutomu Sasao 1 and Alan Mishchenko[removed]Dept. of Computer Science and Electronics, Kyushu Institute of Technology, Iizuka[removed], Japan

LUTMIN: FPGA Logic Synthesis with MUX-Based and Cascade Realizations Tsutomu Sasao 1 and Alan Mishchenko[removed]Dept. of Computer Science and Electronics, Kyushu Institute of Technology, Iizuka[removed], Japan

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Source URL: www.bvsrc.org

Language: English - Date: 2009-07-09 02:20:06
73社団法人 電子情報通信学会 THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS 信学技報 TECHNICAL REPORT OF IEICE

社団法人 電子情報通信学会 THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS 信学技報 TECHNICAL REPORT OF IEICE

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Source URL: www.bvsrc.org

Language: English - Date: 2002-11-23 21:54:00
74An Introduction to Zero-Suppressed Binary Decision Diagrams Alan Mishchenko Department of Electrical and Computer Engineering Portland State University, Portland, OR 97207, USA [removed]; http://www.ee.pdx.edu/~a

An Introduction to Zero-Suppressed Binary Decision Diagrams Alan Mishchenko Department of Electrical and Computer Engineering Portland State University, Portland, OR 97207, USA [removed]; http://www.ee.pdx.edu/~a

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Source URL: www.bvsrc.org

Language: English - Date: 2001-09-30 22:57:32
75FRAIGs: A Unifying Representation for Logic Synthesis and Verification Alan Mishchenko, Satrajit Chatterjee, Roland Jiang, Robert Brayton Department of EECS, University of California, Berkeley {alanmi, satrajit, jiejiang

FRAIGs: A Unifying Representation for Logic Synthesis and Verification Alan Mishchenko, Satrajit Chatterjee, Roland Jiang, Robert Brayton Department of EECS, University of California, Berkeley {alanmi, satrajit, jiejiang

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Source URL: www.bvsrc.org

Language: English - Date: 2005-04-01 15:19:32
76Microsoft Word - iwls07-final.doc

Microsoft Word - iwls07-final.doc

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Source URL: www.bvsrc.org

Language: English - Date: 2007-05-01 11:44:52
77Encoding of Boolean Functions and Its Application to LUT Cascade Synthesis Alan Mishchenko Department of ECE Portland State University Portland, OR 97207, USA [removed]

Encoding of Boolean Functions and Its Application to LUT Cascade Synthesis Alan Mishchenko Department of ECE Portland State University Portland, OR 97207, USA [removed]

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Source URL: www.bvsrc.org

Language: English - Date: 2002-05-15 21:59:58
78Minimization of Average Path Length in BDDs by Variable Reordering Shinobu NAGAYAMA1 Alan MISHCHENKO2  Tsutomu SASAO1,3

Minimization of Average Path Length in BDDs by Variable Reordering Shinobu NAGAYAMA1 Alan MISHCHENKO2 Tsutomu SASAO1,3

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Source URL: www.bvsrc.org

Language: English - Date: 2003-04-24 12:04:31
79Microsoft Word - ASPDAC Support Reduciing final.doc

Microsoft Word - ASPDAC Support Reduciing final.doc

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Source URL: www.bvsrc.org

Language: English - Date: 2005-01-30 12:29:36
80LNCS[removed]Domain Types: Abstract-Domain Selection Based on Variable Usage

LNCS[removed]Domain Types: Abstract-Domain Selection Based on Variable Usage

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Source URL: www.infosun.fim.uni-passau.de

Language: English - Date: 2013-10-30 13:54:10